View UPD16337W_3240503.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1998 data sheet mos integrated circuit m pd16337 64-bit ac-pdp driver the m pd16337 is a high-voltage cmos driver designed for flat display panels such as pdps, vfds and els. it consists of a 64-bit bi-directional shift register (16 bit 4 circuits), 64-bit latch and high-voltage cmos driver. the logic block is designed to operate at 5-v power supply, enabling direct connection to a microcontroller. in addition, the m pd16337 achieves low power dissipation by employing cmos structure while having a high withstand voltage output (150 v, 40 ma max.) features ? built in four 16-bit bi-directional shift register circuits ? data control with transfer clock (external) and latch ? high-speed data transfer (f max. = 20 mhz min. at cascade connection) ? wide operating temperature range (t a = C40 to +85 c) ? high withstand output voltage (150 v, 40 ma max.) ? 5-v cmos input interface ? high withstand voltage cmos structure ? capable of reversing all driver outputs by pc pin ordering information part number package m pd16337gf-3ba 100-pin plastic qfp document no. s12363ej1v0ds00 (1st edition) date published january 1998 n cp(k) printed in japan
m pd16337 2 block diagram pc blk le o 1 note s 64 s 61 s 62 s 63 s 64 l 64 s 1 s 2 s 3 s 4 le l 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a 1 a 2 b 2 a 3 b 3 a 4 b 4 a 1 sr1 s 1 clk clk s 5 . . . . . . . . . . . . . . . . r/l r/l s 61 b 1 b 1 a 2 sr2 s 2 clk s 6 . . . . . . . . . . . . . . . . r/l s 62 b 2 a 3 sr3 s 3 clk s 7 . . . . . . . . . . . . . . . . r/l s 63 b 3 a 4 sr4 s 4 clk s 8 . . . . . . . . . . . . . . . . r/l s 64 b 4 srn: 16-bit shift register note high withstand voltage cmos driver, 150 v, 40 ma (max.)
m pd16337 3 pin configuration (top view) 100 o 42 o 41 o 40 o 39 o 38 o 37 o 36 o 35 o 34 o 33 o 32 o 31 o 30 o 29 o 28 o 27 o 26 o 25 o 24 o 23 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nc v dd2 nc v ss2 nc o 22 o 21 o 20 o 19 o 18 o 17 o 16 o 15 o 14 o 13 o 12 o 11 o 10 o 9 o 8 o 7 o 6 o 5 o 4 o 3 o 2 o 1 nc v dd2 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 nc v dd2 nc v ss2 nc o 43 o 44 o 45 o 46 o 47 o 48 o 49 o 50 o 51 o 52 o 53 o 54 o 55 o 56 o 57 o 58 o 59 o 60 o 61 o 62 o 63 o 64 nc v dd2 nc v ss2 nc clk le b 4 b 3 b 2 b 1 v ss1 nc r/l v dd1 a 1 a 2 a 3 a 4 pc blk nc v ss2 31 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 100-pin plaxtic qfp cautions 1. pin 40 is connected to the lead frame, and therefore must be left open. 2. ensure that the v dd1 , v dd2 , v ss1 and v ss2 pins are all used, and that v ss1 and v ss2 are used at the same potential. 3. to prevent latch up breakdown, the power should be turned on in the order v dd1 , logic signal, v dd2 . it should be turned off in the opposite order.
m pd16337 4 pin description symbol pin name pin number description pc polarity change input 47 pc = l: all driver output invert blk blank input 48 blk = h: all output = h or l le latch enable input 34 automatically executes latch by setting high at rising edge of the clock a 1 to a 4 right data input/output 43 to 46 when r/l = h, a 1 to a 4 : input b 1 to b 4 : output b 1 to b 4 left data input/output 38 to 35 when r/l = l, a 1 to a 4 : output b 1 to b 4 : input clk clock input 33 shift executed on fall r/l shift control input 41 right shift mode when r/l = h sr 1 : a 1 ? s 1 s 61 ? b 1 (same direction for sr 2 sr 4 ) left shift mode when r/l = l sr 1 : b 1 ? s 61 s 1 ? a 1 (same direction for sr 2 sr 4 ) o 1 to o 64 high withstand voltage output 54 to 75, 81 to 130 v, 40 ma max. 100, 6 to 27 v dd1 power supply for logic block 42 5 v 10% v dd2 power supply for driver block 2, 29, 52, 79 30 to 130 v v ss1 logic gnd 39 connect to system gnd v ss2 driver gnd 4, 31, 50, 77 connect to system gnd nc non-connection 1, 3, 5, 28, 30, non-connection 32, 40, 49, 51, ensure that pin 40 is left open. 53, 76, 78, 80
m pd16337 5 truth table 1 (shift register block) input output shift register r/l clk a b h input output note 1 right shift execution h h or l output hold l output note 2 input left shift execution l h or l output hold notes 1. the data of s 57 , s 58 , s 59 , s 60 shifts to s 61 , s 62 , s 63 , s 64 and is output from b 1 , b 2 , b 3 , b 4 at the falling edge of the clock, respectively. 2. the data of s 5 , s 6 , s 7 , s 8 shifts to s 1 , s 2 , s 3 , s 4 and is output from a 1 , a 2 , a 3 , a 4 at the falling edge of the clock, respectively. truth table 2 (latch block) le clk output state of latch block (l n ) h - latch s n data and hold output data hold latch data l hold latch data truth table 3 (driver block) l n blk pc output state of driver block h h h (all driver outputs: h) h l l (all driver outputs: l) l h output latch data (l n ) l l output reversed latch data (l n ) : h or l, h: high level, l: low level
m pd16337 6 timing chart (right shift) clk a 1 (b 4 ) a 2 (b 3 ) a 3 (b 2 ) a 4 (b 1 ) s 1 (s 64 ) s 2 (s 63 ) s 3 (s 62 ) s 4 (s 61 ) s 5 (s 60 ) s 6 (s 59 ) s 7 (s 58 ) s 8 (s 57 ) o 1 (o 64 ) o 2 (o 63 ) o 3 (o 62 ) o 4 (o 61 ) o 5 (o 60 ) o 6 (o 59 ) o 7 (o 58 ) o 8 (o 57 ) le blk pc remark values in parentheses in the above chart are when r/l = l.
m pd16337 7 absolute maximum ratings (t a = 25 c, v ss1 = v ss2 = 0 v) parameter symbol ratings unit logic block supply voltage v dd1 C0.5 to +7.0 v driver block supply voltage v dd2 C0.5 to +150 v logic block input voltage v i C0.5 to v dd1 + 0.5 v driver block output current i o2 40 ma input current i i 25 ma power dissipation p d 1300 note mw operating ambient temperature t a C40 to +85 c storage temperature t stg C65 to +150 c note derate at C13 mw/ c at t a = 25 c or higher recommended operating conditions (t a = C40 to +85 c, v ss1 = v ss2 = 0 v) parameter symbol min. typ. max. unit logic block supply voltage v dd1 4.5 5.0 5.5 v driver block supply voltage v dd2 30 130 v high-level input voltage v ih 0.7 v dd1 v dd1 v low-level input voltage v il 0 0.2 v dd1 v driver output current i oh2 C30 ma i ol2 +30 ma electrical specifications (t a = 25 c, v dd1 = 5.0 v, v dd2 = 130 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit high-level output voltage v oh1 logic, i oh1 = C1.0 ma 0.9 v dd1 v dd1 v low-level output voltage v ol1 logic, i ol1 = 1.0 ma 0 0.1 v dd1 v high-level output voltage v oh21 o 1 to o 64 , i oh2 = C10 ma 123 v v oh22 o 1 to o 64 , i oh2 = C30 ma 110 v low-level output voltage v ol21 o 1 to o 64 , i ol2 = 10 ma 5.0 v v ol22 o 1 to o 64 , i ol2 = 30 ma 15 v input leakage current i il v 1 = v dd1 or v ss1 1.0 m a high-level input voltage v ih 0.7 v dd1 v low-level input voltage v il 0.2 v dd1 v static current dissipation i dd1 logic, t a = C40 to +85 c 100 m a i dd1 logic, t a = 25 c10 m a i dd2 driver, t a = C40 to +85 c 1000 m a i dd2 driver, t a = 25 c 100 m a
m pd16337 8 switching characteristics (t a = 25 c, v dd1 = 5.0 v, v dd2 = 130 v, v ss1 = v ss2 = 0 v, logic c l = 15 pf, driver c l = 50 pf, t r = t f = 6.0 ns) parameter symbol conditions min. typ. max. unit transmission delay time t phl1 clk ? a/b 40 ns t plh1 40 ns t phl2 clk - (le = h) ? o 1 to o 64 180 ns t plh2 180 ns t phl3 blk ? o 1 to o 64 165 ns t plh3 165 ns t phl4 pc ? o 1 to o 64 160 ns t plh4 160 ns rise time t tlh o 1 to o 64 200 ns fall time t thl o 1 to o 64 200 ns maximum clock frequency f max. when data is read, duty 50% 25 mhz t a = C40 to +85 c v dd1 = 4.5 to 5.5 v when a cascade connection is 20 mhz made with a duty of 50% t a = C40 to +85 c v dd1 = 4.5 to 5.5 v input capacitance c i 15 pf timming requirement (t a = C40 to +85 c, v dd1 = 4.5 to 5.5 v, v ss1 = v ss2 = 0 v, t r = t f = 6.0 ns) parameter symbol conditions min. typ. max. unit clock pulse width pw clk 20 ns latch enable pulse width pw le 30 ns blank pulse width pw blk 500 ns pc pulse width pw pc 500 ns data setup time t setup 10 ns data hold time t hold 10 ns latch enable time 1 t le1 20 ns latch enable time 2 t le2 10 ns latch enable time 3 t le3 20 ns latch enable time 4 t le4 10 ns
m pd16337 9 switching characteristics waveform 1/f max. pw le pw clk (h) 50% 50% 50% 50% 50% 50% 50% 50% 50% 90% 10% 50% 50% 50% pw clk (l) t setup t hold t phl1 t plh1 t le1 t le2 t le3 t phl2 t plh2 t le4 v dd1 v ss1 v dd1 clk o n o n a n /b n (input) b n /a n (output) clk le v ss1 v oh1 v ol1 v dd1 v ss1 v dd1 v ss1 v oh2 v ol2 v oh2 v ol2
m pd16337 10 pw blk pw pc t phl3 t plh3 t phl4 t plh4 50% 50 % 50% 50% 90% 10% 10% 90 % v dd1 v ss1 v oh2 v ol2 v dd1 v ss1 v oh2 v ol2 o n pc o n blk
m pd16337 11 package drawings 100 pin plastic qfp (14 20) item millimeters inches d f g i j 0.8 0.6 0.65 (t.p.) 0.15 17.2?.2 q 0.677?.008 0.031 0.024 0.006 0.026 (t.p.) s100gf-65-3ba-3 note each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. c 14.0?.2 0.551 m 0.15 0.006 0.125?.075 0.005?.003 +0.004 ?.003 +0.009 ?.008 a 23.2?.2 0.913 h 0.30?.10 0.012 +0.004 ?.005 l 0.8?.2 0.031 +0.009 ?.008 n 0.10 0.004 p 2.7 0.106 s 3.0 max. 0.119 max. +0.10 ?.05 b 20.0?.2 0.787 +0.009 ?.008 +0.009 ?.008 k 1.6?.2 0.063?.008 r5 ? 5 ? m 80 81 50 100 1 31 30 51 n detail of lead end i j f g h q r p k m l a b cd s
m pd16337 12 recommended soldering conditions this product should be soldered and mounted under the conditions recommended below. for soldering methods and conditions other than those recommended, please contact your nec sales represen- tative. surface mount type for details of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e) . m pd16337gf-3ba soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 230 c, duration: 30 sec. max. ir30-00-2 (at 210 c or above), number of times: twice, time limit: none note vps package peak temperature: 215 c, duration: 40 sec. max. vp15-00-2 (at 200 c or above), number of times: twice, time limit: none note pin partial heating pin partial temperature: 300 c max., duration: 10 sec. max., time limit: none note note for the storage period after dry-pack decapsulation, storage conditions are max. 25 c, 65% rh. caution use of more than one soldering method should be avoided (except in the case of pin partial heating). references nec semiconductor device reliability/quality control system (iei-1212) quality grade on nec semiconductor devices (c11531e)
m pd16337 13 [memo]
m pd16337 14 [memo]
m pd16337 15 [memo]
m pd16337 2 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5

▲Up To Search▲

Price & Availability of UPD16337W

	To Download UPD16337W Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .